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[SCM] bcd_conv

Description: convert.asm: 1.From ASCII resp. BCD to binary 2.From binary to ASCII resp. BCD 3.From binary to Hex-ASCII Bin_Bcd.c: uchar BcdToBin(uchar val) uchar BinToBcd(uchar val) -convert.asm : 1.From ASCII resp. BCD 2.From binary to binary t o ASCII resp. BCD 3.From binary to Hex-ASCII Bin _Bcd.c : uchar BcdToBin (uchar val) uchar BinToBcd (uch ar val)
Platform: | Size: 5120 | Author: jack | Hits:

[ELanguage] rs-codec-8-4

Description: encode.v The encoder syndrome.v Syndrome generator in decoder berlekamp.v Berlekamp algorithm in decoder chien-search.v Chien search and Forney algorithm in decoder decode.v The top module of the decoder inverse.v Computes multiplication inverse of an Galois field element test-bench.v The test fixture, and some brief notes on using the modules. data-rom.v A simple data source for testing run For those intelligence-challenged who can t run verilog LGPL The license -encode.v syndrome.v Syndrome generator in decoder al berlekamp.v Berlekamp gorithm in decoder chien- search.v Chien searc h and Forney in decoder algorithm decode.v The t op module of the decoder inverse.v Computes intercommunication tiplication inverse of an element over Galois field test-bench.v The test fixture. and some brief notes on using the modules. data- rom.v A simple data source for testing run For th PNA intelligence-challenged who can not run veri The log LGPL license
Platform: | Size: 45056 | Author: zs8292 | Hits:

[VHDL-FPGA-Verilog] rs_decoder_31_19_6.tar

Description: Hard-decision decoding scheme Codeword length (n) : 31 symbols. Message length (k) : 19 symbols. Error correction capability (t) : 6 symbols One symbol represents 5 bit. Uses GF(2^5) with primitive polynomial p(x) = X^5 X^2 + 1 Generator polynomial, g(x) = a^15 a^21*X + a^6*X^2 + a^15*X^3 + a^25*X^4 + a^17*X^5 + a^18*X^6 + a^30*X^7 + a^20*X^8 + a^23*X^9 + a^27*X^10 + a^24*X^11 + X^12. Note: a = alpha, primitive element in GF(2^5) and a^i is root of g(x) for i = 19, 20, ..., 30. Uses Verilog description with synthesizable RTL modelling. Consists of 5 main blocks: SC (Syndrome Computation), KES (Key Equation Solver), CSEE (Chien Search and Error Evaluator), Controller and FIFO Register. -Hard-decision decoding scheme Codeword l KV (n) : 31 symbols. Message length (k) : 19 symbols. Error correction capability (t) : 6 symbols One symbol represents five bit. Uses GF (2 ^ 5) with primitive polynomial p (x) = x ^ x ^ 5 2 1 Ge nerator polynomial. g (x) = a ^ a ^ 15* 21 ^ 6 a X* X ^ a ^ 15 2* X ^ a ^ 3 25* X ^ a ^ 4 17 5* X ^ a ^ 18 ^ 6 X* a* X 30 ^ 7 ^ a ^ 20* X ^ a ^ 23 8* X ^ a ^ 9* 27 X 10 ^ a ^ 24* 11 ^ X ^ X 12. Note : a = alpha, primitive element in GF (2 ^ 5) and a ^ i is the root of g (x) for i = 19, 20, ..., 30. Uses Verilog description with synthesizab le RTL modeling. Consists of five main blocks : SC (Syndrome Computation), KES (Key Equation Solver). CSEE (Chien Search and Error Evaluator) Controller and FIFO Register.
Platform: | Size: 14336 | Author: 许茹芸 | Hits:

[Internet-Network] Verilog

Description: Verilog实现的以太网接口源程序代码-Realize the Ethernet interface Verilog source code
Platform: | Size: 129024 | Author: zhl | Hits:

[VHDL-FPGA-Verilog] ethernet.tar

Description: 以太网的vhdl和verilog代码，供大家学习-Ethernet VHDL and Verilog code for everyone to learn
Platform: | Size: 934912 | Author: sunlee | Hits:

[SCM] TFTDriverNew_V2

Description: TFT液晶屏驱动模块Verilog源码。实现方法：XC95288+K6R4008，K6R4008主要用作帧缓冲区，此模块仅支持256色-TFT LCD driver module Verilog source code. Realization: XC95288+ K6R4008, K6R4008 mainly used as a frame buffer, this module only supports 256 colors
Platform: | Size: 3072 | Author: zhangming | Hits:

[VHDL-FPGA-Verilog] test_uart

Description: uart VHDL code : include tx,rx,parity bit control
Platform: | Size: 13312 | Author: byungchan | Hits:

[VHDL-FPGA-Verilog] TFT

Description: 基于FPGA的实验。使用FPGA直接控制TFT彩屏，达到显示彩条的效果。使用FPGA连接TFT控制器，使显示一组汉字或一幅图像。 -FPGA-based experiment. FPGA to directly control the use of TFT color display to show the effect of color. TFT controller using FPGA connected to a group of Chinese characters displayed or an image.
Platform: | Size: 1024 | Author: 贺欧 | Hits:

[Software Engineering] DDCFPGA

Description: 针对DVB-T标准ETSI EN 300 744 V1.5.1,设计了可用于DVB-T接收整机的多速率DDC模块,并在FPGA中仿真实现.在复用数字振荡混频模块的基础上,根据输入信号的不同带宽(6M/8MHz)选择不同的抽取滤波器组完成抽取因子为3或4的多速率处理任务,利用两级半带滤波器(HBF)级联完成4倍抽取滤波,单级奈奎斯特滤波器完成3倍抽取滤波.-For the DVB-T standard ETSI EN 300 744 V1.5.1, designed for DVB-T receiver machine multi-rate DDC module, and the simulation in the FPGA implementation. Numerical oscillation in the complex mixer module, based on the input signals of different bandwidths (6M/8MHz) choose a different group of complete decimation filter extracted factor 3 or 4 of the multi-rate processing tasks, using two half-band filter (HBF) cascade to complete four times decimation filter, single-stage Chennai Nyquist filter to complete three times the decimation filtering.
Platform: | Size: 309248 | Author: 王楚宏 | Hits:

[Software Engineering] plugin-tut_timing_verilog_Lab2

Description: manual for time analysis and testing the critical path in verilog FPGA using Accumulator design
Platform: | Size: 389120 | Author: ahmed | Hits:

[VHDL-FPGA-Verilog] T_light

Description: A verilog HDL program to simulate a traffic light condition at a T-junction.
Platform: | Size: 1024 | Author: wildchild4u | Hits:

[VHDL-FPGA-Verilog] ldpc_encoder_802_3an_latest.tar

Description: 适用于10GBase-T的以太网(802.3an协议)LDPC, VERILOG语言编写，可以应用在LATTICEXP2系列芯片上，基于Gallager算法。-LDPC encoder for 10GBase-T Ethernet (802.3an), based on Gallager s A algorithm
Platform: | Size: 620544 | Author: liang | Hits:

[Other] video_of_VERILOG

Description: the video about verilog source t he video about verilog source the video about verilog source-the video about verilog source the video about verilog source the video about verilog source the video about verilog source
Platform: | Size: 4146176 | Author: 马力 | Hits:

[VHDL-FPGA-Verilog] MIPS1CYCLE

Description: MIPS single-cycle processor design in verilog.Instruction memory to the design and initialise it with your assembly code-a. Load the data stored in the X and Y locations of the data memory into the X and Y registers. b. Add the X and Y registers and store the result in the Z register. c. Store the data from the Z register into the Z memory location. d. Load the data in the Z memory location into the T register.
Platform: | Size: 2048 | Author: chenghao wei | Hits:

[VHDL-FPGA-Verilog] mtspeed

Description: m法t法编码器测速 verilog语言 m法采样时间可调 t法间隔周期可调-m method t method m encoder velocity verilog language law law sampling time interval period adjustable adjustable t
Platform: | Size: 1024 | Author: 王程序 | Hits:

[VHDL-FPGA-Verilog] 86verilog

Description: 以FPGA 芯片为平台构建了数字信号滤波实时处理模块, 给出了 50Hz 陷波器的切比雪夫Ê 型 IIR 数字 滤波器 4 阶级联的结构, 提出了对滤波器系数量化的逼近方法, 完成了基于 FPGA 的陷波器实现, 并成功地实现了 对含有工频 50Hz 噪声干扰的心电信号的滤波处理, 通过与M at lab 计算所得到的滤波处理效果进行比较分析, 结 果表明: 基于FPGA 采用切比雪夫Ê 型 4 级级联结构的 IIR 数字滤波器的误差满足设计要求-　W ith the development of the techno logy of VL S I, the techno logy fo r digital signal p rocessing has developed rap idly . In th is paper, the arch itecture of 50Hz four th2 o rder Chebyshev′ s ModelÊ digital f ilter is show n . In the same t i me, themethod fo r f ilter coeff icient quant if icat i on is p resented . How ever, the f ilter based on FPGA is i mp lemented . The f ilter can p rocess digital signal successfully and its perfo rmance sat isf ies w ith design requirement .
Platform: | Size: 15360 | Author: 任伟 | Hits:

[VHDL-FPGA-Verilog] Verilog

Description: 七段数码管译码器.(Verilog)[FPGA]第一个Verilog程序,七段共阴数码管摸索了好几天,终于能完成敲入代码、综合、仿真、绑定引脚至下载的全套工作了 -. 七段数码管的lookup table module SEG7_LUT ( input [3:0] iDIG, output reg [6:0] oSEG ) always@(iDIG) begin case(iDIG) 4 h1: oSEG = 7 b1111001 //---t---- 4 h2: oSEG = 7 b0100100 // | | 4 h3: oSEG = 7 b0110000 // lt rt 4 h4: oSEG = 7 b0011001 // | | 4 h5: oSEG = 7 b0010010 //---m---- 4 h6: oSEG = 7 b0000010 // | | 4 h7: oSEG = 7 b1111000 // lb rb 4 h8: oSEG = 7 b0000000 // | | 4 h9: oSEG = 7 b0011000 //---b---- 4 ha: oSEG = 7 b0001000 4 hb: oSEG = 7 b0000011 4 hc: oSEG = 7 b1000110 4 hd: oSEG = 7 b0100001 4 he: oSEG = 7 b0000110 4 hf: oSEG = 7 b0001110 default: oSEG = 7 b1000000 endcase end endmodule
Platform: | Size: 1024 | Author: 王林林 | Hits:

[Mathimatics-Numerical algorithms] Verilog-for-SDcard

Description: 啊，我前段时间编这个，当时晕的，用verilog做SD卡的例子网上很少，我当时找了好多C语言的，主要是知道发送命令的顺序和控制流程，你可以先做好SPI部分，运用C程序的发送命令顺序，把SD卡初始化，提取SD卡特定寄存器看成不成功，其实只要SPI时序没问题，一般没问题，之后用Winhex看看你的SD卡的FAT系统，网上有学习用的资料，好好算算数，之后应该可以做到直接读写SD卡，但若想随意读写SD卡工作量太大了，我还没这勇气-Ah, I make this a while ago, at that time, faint, SD card example using verilog do seldom online, I was looking for a lot of C language, mainly know the order of sending command and control process, you can just do SPI part, using the C program to send the command sequence, the SD card initialization, extract the SD carter register as you don t succeed, in fact, as long as SPI timing problem, generally no problem, then use Winhex see your SD card FAT system, online learning with data, to calculate arithmetic, after SD card should be able to do it directly, speaking, reading and writing, but to read and write at random SD card workload is too big, I haven t the courage
Platform: | Size: 5120 | Author: 王宇 | Hits:

[Program doc] 443407739SPI_Code(Verilog)

Description: spi_slave_model tb_spi_top wb_spi_top SPI总线-Please don t borrow random
Platform: | Size: 229376 | Author: 许进 | Hits:

[Other] diversity

Description: THIS A I GR CODE G]T ANIM
Platform: | Size: 59392 | Author: niaz | Hits:
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